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Altera_Forum
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11 years ago

Trouble Getting DDR SDRAM Working in Qsys

Hello,

I'm making a board with a Cyclone IV FPGA, and having some trouble getting my DDR signals to be what they should be. I have a clock bridge between a Nios II Processor and my DDR SDRAM controller with ALTMEMPHY. When I probe the nCS signal it appears to be stuck high. When I program it, it may drop low for a few clock cycles, but that's it. DQ pins are stuck low. I'm thinking maybe it's stuck in reset, but I tried exporting both reset_n signals, forced them to '1' and I still get the same issue. My refclk is 10MHz, and I know that works. Should the DQ pins or nCS be switching values if it's working correctly without nios running on it? I'm trying to download my .elf but since the DDR doesn't seem to be working, I can't get the instructions/data in there. If anyone has an idea to try, it would really help me out!

Thanks,

- Rob

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Before you consider the internal logic - how confident are you in your hardware? Are you happy the board has been assembled correctly? Do you have experience putting such an FPGA design together, using the IP you mention?

    To confirm your design and build you might try putting together a much simpler design which just attempts to toggle some of the relevant pins so you can monitor the connections to the external memory. Once you're happy that your hardware platform is correct we can consider using something more useful.

    Regards,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    This is a last ditch effort to try to get an Alliance Memory DDR1 chip ( http://www.alliancememory.com/pdf/ddr1/128m-as4c8m16d1.pdf ) working with a Cyclone IV FPGA (EP4CE22F17C6) using ALTMEMPHY. The FPGA and RAM are less than 3" apart, traces are length matched, and the design is essentially identical to an Altera reference design. The Alliance RAM doesn't have a memory preset in the megafunction, but I've set all the parameters to be within spec, trying to run at 120 MHz (have also tried 100 MHz). I've gone through all clock phases (0, 90, 180, 270), and 180 looks to match up the best under the scope but still doesn't seem to work. Have tried two chips in case one was a dud. Clock signals cross nicely, no critical warnings in Quartus when compiling. Using normal compilation effort, and standard fit under fitter settings. I've also tried making a smaller program with ONLY a DDR megafunction for debugging.

    I am claiming it doesn't work because it fails verification when I try to upload a NiosII elf to it. Also, the local_init_done signal never goes high. I've tried using the Debug GUI program, doing a functional simulation, SignalTap, and looking at it under a scope, but I'm not sure what is preventing it from working. It seems as if it is not coming out of the calibration stage. I've tried to compare the same program with modelsim and under the scope, and I've attached a few pictures. You can see there is a small section at the end which isn't happening on the board that is happening in modelsim, and after that is where the pnf goes high. It finishes it's third rrp_sweep stage and then stops - why? I've also attached the startup sequences for Altera and the memory manufacturer.

    I'm just kind of out of ideas at this point, if anyone has a hunch, I would be grateful. Thanks

    Scope shot is from the CASn signal.