Trouble enabling HPC to FPGA bridge on Cyclone V SoC
I'm working on a bare metal application on a Cyclone V SoC (5CSEBA6U23I7NDK).
Things are going reasonably well, I have the u-boot SPL booting from eMMC on power-up and it's loading my application....
OK, after many hours of head scratching I think I found my problem.
To use the HPS->FPGA slave you need to set bit 3 of the remap register located at address 0xFF800000. To use the lightweight bridge you need to set bit 4 of this register.
If you are booting up with U-boot, can you try to execute "bridge enable", it is one of the cmd available in U-boot. Can check whether it is available by typing help in U-boot.
After execute "bridge enable", can use md to check the address content. Example to check the address content, md 0xC0000000.
I'm only using the u-boot SPL, not the full boot loader. The SPL just does initial configuration of the SDRAM and some other areas of the HPS and then jumps to my code. The SPL doesn't have any type of user interface, so I can't use it to configure the bridge.
I've been doing more investigation into this issue, but am still getting bus fault exceptions any time I try to access the memory space of either the HPS->FPGA bridge or the lightweight bridge.
I've found that even trying to access the register space in the lightweight bridge results in a bus fault exception. For example, the read only ID registers located in the lightweight bridge at 0xFF401FD0, 0xFF401FE0, etc. Attempting to read any of these registers results in a bus fault.
I have confirmed that the FPGA image is properly loaded and the FPGA is in user mode. I also confirmed that I have taken the two bridges I'm trying to use out of reset in the reset manager. I have the l3_main_clk enabled and running at 400MHz, the l4_mp_clk clock enabled and running at 100MHz, and I've got both the h2f_axi_clock and h2f_lw_axi_clock connected to running clocks in my FPGA design.
I replaced my own avalon slave module in the qsys system with a dual port internal RAM block. That removes any of my own design from the qsys system for now. Here's what my qsys design currently looks like, I have attached the qsys file as well.
I'm pretty stumped by this. Let me know if you can think of anything else that I could try.
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