Tristate performance degradation in Qsys

Hi,

I migrated from SOPC Builder to Qsys, but this step reduced the overall system performance.

I discovered that the Qsys tristate connection (tristate bridge + tristate pin sharer + generic tristate controller) is slower than the SOPC tristate bridge (see the waveform), so it introduces a longer read/write latency with my external memory (which obviously decrease the system performance).

After that I try to optimase the performance of Qsys tristate connection, but without success (it is still slower than the SOPC). :mad:

The SOPC settings are:

- incoming signals are registered

- setup time: 30ns

- read wait: 30ns

- write wait: 30ns

- hold time: 0ns

- read latency for pipelined transfers: 0

- active chipselect trough readlatency: deselected

- max pending read transactions: 0

The Qsys settings are:

- setup time: 30ns

- read wait: 30ns

- write wait: 30ns

- hold time: 0ns

- max pending read transations: 1 (0 is not allowed)

- Turnaround time: 0

- read latency: 1 (if read latency is set to 0, the read result is corrupted)

- active chipselect trough readlatency: deselected

Has anyone run into the same problem?

Best regards.

Micio