Forum Discussion
JMedi
New Contributor
7 years agoTriple speed example design for Cyclone V GT dev kit
The board update portal example project use ETH but use old Quartus version and It can't build meeting timing constraint.
1 Reply
- Deshi_Intel
Regular Contributor
HI,
Feel free to check out below other 2 Cyclone V TSE reference design link.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an647.pdf
https://fpgacloud.intel.com/devstore/platform/14.0.0/Standard/triple-speed-ethernet/
Thanks.
Regards,
dlim