Tri-state output and OpenDrain-output in FLEX 10KA

Hi, Andries! Thanks for answer.

I am reprogramming now the old project on the chip FLEX 10K30A and wont to use Verilog HDL. The FPGA connects to RAM with the tri-state buses in 32-bits. When I implement the primitive TRI(in, oe, out), FPGA forms only 0,z states (It was open drain, I think). And all was OK with 0,1,z states when I implemented graphic primitive TRI from library c:\maxplus2\max2lib\prim in the graphic’s mode (It was full tri-states output, I think). In both cases I used TRI primitive. Why does it occur? Why I can’t work with tri-state buses in Verilog HDL and can only in *.gdf? What is wrong?

Best regards,

Serhiy.