Transmit 2 bits of 1MHz (modulation)

Hi,

You better first try your design in quartus and it will tell you if it then fits any other device.

It is not clear what modulation scheme you want to do. You haven't stated your carrier frequency(this is different from bandwidth) and you haven't stated your bit rate.

If your bits are available as input then you need to map them to symbols then generate a carrier(sinusoid) at the target frequency then multiply your symbols with the carrier(mult can be complex or not depending on your modulation scheme) then convert it to analogue and through the cable...

edit: you will also need pulse shaping filter to avoid ISI

Hi KAZ, thanks for your answer.

For my design I have 2 binari TTL inputs (that correspond to 3 levels of voltage) and they can change with a frequency of 1MHz. I can modulate one signal using PWM to transmit the 3 levels?

For example:

- Frequency of the PWM = 25MHz

- First level: Duty cycle at 25%

- Second level: Duty cycle at 50%

- Third level: Duty cycle at 75%

The comunication is always digital. Is easy this modulation/demodulation using one low cost MAX II ? Do you recommend using VHDL or graphic language?

Thanks!

Hi,

PWM is much easier than other types of modulation. As you said you will map the 2 bit input to the 3 voltage levels using a simple mux. I assume your input clk is 100MHz then you can produce 25MHz at 25%, 50% and 75% duty cycle using simple counter. Then you switch out the generated clocks as per incoming levels.

I am not that sure about demodulation plan and would like to learn from your work. I assume it will be straight forward if the Tx/Rx clocks are synchronised

I suggest the following process to generate the duty cycles(code not tested)

signal count : integer range 0 to 3 := 0;

------

process(reset,clkin) -- 100MHz clkin

begin

if(reset = '1')then

count <= 0;

clkout <= '0';

clk1 <= '0'; -- 25MHz, 25% duty

clk2 <= '0'; -- 25MHz, 50% duty

clk3 <= '0'; -- 25MHz, 75% duty

elsif(rising_edge(clkin))then

count <= count + 1;

case count is

when 0 => clk1 <= '1'; clk2 <= '1'; clk3 <= '1';

when 1 => clk1 <= '0'; clk2 <= '1'; clk3 <= '1';

when 2 => clk1 <= '0'; clk2 <= '0'; clk3 <= '1';

when 3 => clk1 <= '0'; clk2 <= '0'; clk3 <= '0';

when others => null;

end case;

case input_level is

when "00" => clkout <= clk1;

when "01" => clkout <= clk2;

when "10" => clkout <= clk3;

when others => null;

end case;

end if;

end process;