MiguelAvina
New Contributor
3 years agoTransceiver Support Cyclone IV - How to implement the PCIE hard IP for Cyclone IV GX (2)
Hi,
I posted a while ago a question on:
"
Is there example code and IP that they we can implement in QSYS for PCIE
hard IP for Cyclone IV GX ?
"
I got the following link: Cyclone V Hard IP for PCI Express User Guide (intel.com)
However, we are wanting to move forward with Cyclone IV GX devices. This UG is for Cyclone V.
1. Is this applicable to the Cyclone IV?
I found the user guide the the IP Compiler for PCIE User guide which I believe will support the Cyclone IV. With that I could really use and example design to share with the customer. I was unable to find one supported in V18.1 lite
2. Could anyone please provide this example design to share with the customer?
Thanks!