Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorTransceiver CDR Question
Hi I want build a design where the FPGA will be receiving 10-bit serial data using one XCVR and a separate clock is provided which corresponds to the 10-bit parallel clock (e.g. 100 MHz clock f...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Just to clarify, when I generate the XCVR related blocks (PHY, PLL, etc.) thru Magawizard, the MIF is not generated then? I would need to do a full design compilation to get the MIF files? --- Quote End --- After successful compilation, you can look into the reconfig_mif folder in the project directory. You can refer to Altera Transceiver PHY IP Core User Guide -> "MIF Generation" section for further info.
