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Altera_Forum
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11 years ago

Transceiver CDR Question

Hi I want build a design where the FPGA will be receiving 10-bit serial data using one XCVR and a separate clock is provided which corresponds to the 10-bit parallel clock (e.g. 100 MHz clock f...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi,

For CDR dynamic reconfiguration, it is recommended for you to use to MIF file to reconfigure the CDR. Quartus II will generate one MIF for each transceiver configuration after successful compilation.