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Altera_Forum
Honored Contributor
Honored ContributorTransceiver CDR Question
Hi I want build a design where the FPGA will be receiving 10-bit serial data using one XCVR and a separate clock is provided which corresponds to the 10-bit parallel clock (e.g. 100 MHz clock f...
Altera_ForumHonored Contributor
Honored ContributorWith regard to the CDR reconfiguration, which specific parameters need reconfiguration? I'm assuming it's the channel PLL settings in my case since the input refclk to CDR can change on the fly. Where are these settings listed and how do I figure out what new settings to apply for each different refclk freq (e.g. ranging from 650MHz to 3GHz)?
