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Altera_Forum
Honored Contributor
Honored ContributorTransceiver CDR Question
Hi I want build a design where the FPGA will be receiving 10-bit serial data using one XCVR and a separate clock is provided which corresponds to the 10-bit parallel clock (e.g. 100 MHz clock f...
Altera_ForumHonored Contributor
Honored Contributor"BTW, when the refclk changes, I assumed the PLL inside the CDR block would simply lose lock and with a reset, it would gain a lock again. Is this not true? "
The CDR should lose lock to data. But I am not sure if it will lose lock to refclk or not. It is advisable to reset the CDR after reconfiguring it.
