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Altera_Forum
Honored Contributor
Honored ContributorTransceiver CDR Question
Hi I want build a design where the FPGA will be receiving 10-bit serial data using one XCVR and a separate clock is provided which corresponds to the 10-bit parallel clock (e.g. 100 MHz clock f...
Altera_ForumHonored Contributor
Honored ContributorSo you recommend using a reconfig controller for XCVR because the refclk frequency could change. Do you have any recommendation of how I could detect the refclk frequency change? I will not get this info (i.e. no separate signals available) from the transmitting side.
BTW, when the refclk changes, I assumed the PLL inside the CDR block would simply lose lock and with a reset, it would gain a lock again. Is this not true?
