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Altera_Forum
Honored Contributor
16 years agoTrack signal in Verilog testbench for limited time
Hi everybody,
And TGIF !! (Thank goodness its friday, I see a beer in my future !!). A Verilog question; I want to track a signal at every clock edge in my testbench, but only when I activate a "switch" variable. Such as: v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} st1\:*{behavior:url(#default#ieooui) } #100 activate_signal_tracking = 1'b1; test_status = signal_to_track; #100 activate_signal_tracking = 1'b0; So I want test_status to get the value of signal_to_track at every clock edge, but only while the activate_signal_tracking is set. It would be good be able to track different signals also. Not quite to simple I have found after trying various ideas, seems like I need a verilog task which I turn on and off somehow ? The monitor statement will print changes of the variable to the screen, but I want to track the test status. Thanks a bunch for the help, whoever gives the right answer and is close to Freiburg Germany gets a beer from me tonight, lol !! :) Have a good weekend ! Eric2 Replies
- Altera_Forum
Honored Contributor
Hello Srini,
Just got back from vacation, thus the late reply. Thats pretty much how I wrote the testbench code, thanks a bunch !! Cheers, Eric - Altera_Forum
Honored Contributor
Use always block with if conditions. Such as:
If you use SystemVerilog you can also use the iff gating as in:always @(posedge clk) begin : track_it if (activate_signal_tracking) begin : active_track test_status = <my_path>.signal_to_track; // .. more such signals to track if needed end : active_track end : track_it
HTH Srini www.cvcblr.com/blogalways @(posedge clk iff activate_signal_tracking) begin : track_it test_status = <my_path>.signal_to_track; // .. more such signals to track if needed end : track_it