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Honored Contributor
Honored ContributorTrack signal in Verilog testbench for limited time
Hi everybody, And TGIF !! (Thank goodness its friday, I see a beer in my future !!). A Verilog question; I want to track a signal at every clock edge in my testbench, but only when I act...
Altera_ForumHonored Contributor
Honored ContributorUse always block with if conditions. Such as:
always @(posedge clk) begin : track_it
if (activate_signal_tracking) begin : active_track
test_status = <my_path>.signal_to_track;
// .. more such signals to track if needed
end : active_track
end : track_it
always @(posedge clk iff activate_signal_tracking) begin : track_it
test_status = <my_path>.signal_to_track;
// .. more such signals to track if needed
end : track_it
