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Altera_Forum's avatar
Altera_Forum
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15 years ago

Track signal in Verilog testbench for limited time

Hi everybody, And TGIF !! (Thank goodness its friday, I see a beer in my future !!). A Verilog question; I want to track a signal at every clock edge in my testbench, but only when I act...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Use always block with if conditions. Such as: 


always @(posedge clk) begin : track_it
  if (activate_signal_tracking) begin : active_track
   test_status = <my_path>.signal_to_track;
   // .. more such signals to track if needed
  end : active_track
end : track_it

If you use SystemVerilog you can also use the iff gating as in: 


always @(posedge clk iff activate_signal_tracking) begin : track_it
   test_status = <my_path>.signal_to_track;
   // .. more such signals to track if needed
end : track_it

HTH

Srini

www.cvcblr.com/blog