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Honored Contributor
Honored ContributorTrack signal in Verilog testbench for limited time
Hi everybody, And TGIF !! (Thank goodness its friday, I see a beer in my future !!). A Verilog question; I want to track a signal at every clock edge in my testbench, but only when I act...
Altera_ForumHonored Contributor
Honored ContributorHello Srini,
Just got back from vacation, thus the late reply. Thats pretty much how I wrote the testbench code, thanks a bunch !! Cheers, Eric
