Forum Discussion
Altera_Forum
Honored Contributor
14 years agoPORT
( clOCK : IN STD_LOGIC; ce : IN STD_LOGIC; rst : IN STD_LOGIC; d1: BUFFER STD_LOGIC_VECTOR (3 DOWNTO 0); clk_2: OUT STD_LOGIC ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! END mod_mod; -- Architecture Body ARCHITECTURE mod_mod_architecture OF mod_mod IS SIGNAL M: STD_LOGIC; BEGIN PROCESS (clock,rst,M) BEGIN IF (rst = '0') THEN d1 <= "0000"; ELSIF (clOCK 'EVENT AND clOCK='1') THEN IF (ce = '0') THEN d1<= "0000" ; ELSE d1<= d1 + '1'; M<= '0'; END IF; IF d1= "1001" THEN d1<= "0000"; M<= '1'; END IF; END IF; clk_2<=M; END PROCESS; end mod_mod; I want ce to perform the function of start and stop.I want it to be like if i press ce switch it should change the logic from 1 to 0 to purse and for the next state to start after pressing same ce switch.