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Altera_Forum's avatar
Altera_Forum
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16 years ago

To change external memory access time?

Hello, I have a board with Nios using external SRAM built in two flavors: the one is fast 10ns SRAM the other is a battery-backed 70ns SRAM. The boards will have different software to work on ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The number of wait states for an SRAM are fixed when the SOPC builder project compiles.

The only way around this that I can see is to write your own component in HDL for the SRAM, and use the wait_request signal to pause the master. Your HDL component could contain a register to configure the number of cycles to keep the wait_request signal enabled for each access.