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Altera_Forum's avatar
Altera_Forum
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15 years ago

To build a FIFO using SRAM

Hi, I would like to build a DCFIFO using a SRAM chip on DE2-115. Any idea on where i should start? I know SRAM reads and writes on a different clock cycle as the dataIn and dataOut share t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Err.. isn't the part on the DE2-115 a 10 ns access time part?

IS61WV102416BLL-10

Anyway, it supports back to back write operation, so he can write at 100 or 125 MHz.

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From the user manual of Terasic, it says the SRAM has maximum performance of up to 125MHz under condition of standard 3.3V....

so i thought 1/125MHz = 8ns ?? no?

And what do you mean by "back to back" ? how does it work?

Michael