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Honored Contributor
Honored ContributorTo build a FIFO using SRAM
Hi, I would like to build a DCFIFO using a SRAM chip on DE2-115. Any idea on where i should start? I know SRAM reads and writes on a different clock cycle as the dataIn and dataOut share t...
Altera_ForumHonored Contributor
Honored ContributorPlease take a look at write cycle number 4 in page 16. Note that tSA, tHA and tHD can be as low as zero. My interpretation is that even the UP and LB pulses shown are not needed, it suffices to keep them low during the write burst, along with CE, WE and OE. And then, you only need to make sure tSD is respected relative to the next address change.
