Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorTip/suppornt on debugging a VHDL project on Altera
Hi I have some experience on hdl coding, but none on FPGA debugging. (which does not necessarily mean the problem may not be in my HDL coding... ;) ) I´m facing a weird (imho) situation ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Here are my concerns: 1. It looks like you're using "clk_spi_flash" in logic - is this really a clock, or is it some form of synchronised signal? This can cause all sorts of problems if it really is a clock, which wont be apparent in simulation 2. You cannot compare signals to 'Z' on real hardware. What kind of logic circuit can detect that? Again, this would work fine in simulation, but not work in hardware. --- Quote End --- Regarding (1): Yes, it is really a clock. I need to synchronize the setting of int_flash_en with its edge. clk_spi_flash is about 4x slower than clk. Is there a better/correct way to handle this synchronizing? May it be my problem's root? Regarding (2): Ok, shame on myself... :( Yet, do you think I should try to code a state machine to ease coding and analysis? I thought it would be a simple code so I decided not to build a state machine, but it got more complex now I'm about to reconsider it. Thanks and regards
