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Altera_Forum
Honored Contributor
Honored ContributorTip/suppornt on debugging a VHDL project on Altera
Hi I have some experience on hdl coding, but none on FPGA debugging. (which does not necessarily mean the problem may not be in my HDL coding... ;) ) I´m facing a weird (imho) situation ...
Altera_ForumHonored Contributor
Honored ContributorHere are my concerns:
1. It looks like you're using "clk_spi_flash" in logic - is this really a clock, or is it some form of synchronised signal? This can cause all sorts of problems if it really is a clock, which wont be apparent in simulation 2. You cannot compare signals to 'Z' on real hardware. What kind of logic circuit can detect that? Again, this would work fine in simulation, but not work in hardware.
