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Altera_Forum
Honored Contributor
Honored ContributorTip/suppornt on debugging a VHDL project on Altera
Hi I have some experience on hdl coding, but none on FPGA debugging. (which does not necessarily mean the problem may not be in my HDL coding... ;) ) I´m facing a weird (imho) situation ...
Altera_ForumHonored Contributor
Honored Contributor>>There are no latches as it is a clocked process.<< . Yes of course. I didn't notice the clock. How ever you might try with Tricky's suggestion, you can try to do the change and test your design.
