Tip/suppornt on debugging a VHDL project on Altera

Hello cprodrigues, I see that there could be latches produced from the above code. This is because the signals are not assigned values in all reachable statements. Please correct that. Latches are not preferred in a very good logic design as they have unpredictable results or they generate glitches during the operation.

In the mean time you can design a state machine that does the above job in a very nice and glitch free way.

I see that int_flash_en signal will have very tight timing as you are checking the signal with in the process as well as assigning the same signal with different value. Please check your timing. This could be also a problem. all the best.