Tip/suppornt on debugging a VHDL project on Altera

Hello everybody

Thanks for answering that, and sorry if my mistakes were too basic.

Here follows the whole code for the process, if you may take a look. The signals are touched just after "WRITE OPERATION" comment.

In the meantime, I´m going to check the rst in the sensitivity list and see how it works.

Thanks again

-- Flash protocol handling process

flash_process(clk)

begin if(rst='1') thenflash_data <= "ZZZZZZZZ";

flash_opcode <= X"0";

flash_addr <= X"000000";

int_flash_en <= '0';

flash_erase_running <= '0';

flash_read_running <= '0';

flash_write_running <= '0';

etcmiv_data <= "ZZZZZZZZ";

etcmiv_data_rdy <= 'Z';

etcmiv_data_rdy_detected <= '0';

[/INDENT] -- ERASE OPERATION

elsif(rising_edge(clk)) thenif((etcmiv_flash_erase ='1') or (flash_erase_running= '1'))then

[/INDENT] if(etcmiv_flash_erase ='1') then -- first time

[/INDENT][/INDENT] flash_erase_running <= '1';

flash_addr <= erase_addr;

case(int_etcmiv_opcode) is

[/INDENT][/INDENT][/INDENT] when ERASE_INIT_PARAM_T | ERASE_DEF_PARAM_T | ERASE_AGC_T | ERASE_BPR_T =>

[/INDENT][/INDENT][/INDENT][/INDENT] flash_opcode <= ERASE_4K_OP;

[/INDENT][/INDENT][/INDENT][/INDENT] when ERASE_NUC_T | ERASE_MENU_T =>

[/INDENT][/INDENT][/INDENT][/INDENT] flash_opcode <= ERASE_64K_OP;

[/INDENT][/INDENT][/INDENT][/INDENT] when others => NULL;

[/INDENT][/INDENT][/INDENT][/INDENT] end case;

[/INDENT][/INDENT][/INDENT][/INDENT] else -- not first time, erase operation started

[/INDENT][/INDENT] if((clk_spi_flash = '1') and (int_flash_en = '0'))then -- flash_en should change only on a sck falling edge

[/INDENT][/INDENT][/INDENT] int_flash_en <= '1';

[/INDENT][/INDENT][/INDENT][/INDENT] elsif(flash_done = '1') then

[/INDENT][/INDENT][/INDENT] int_flash_en <= '0';

flash_erase_running <= '0';

end if;

[/INDENT][/INDENT][/INDENT][/INDENT] end if;

[/INDENT][/INDENT] -- WRITE OPERATION

elsif((etcmiv_flash_write = '1') or (flash_write_running = '1')) then

if(etcmiv_flash_write = '1') then -- first time

[/INDENT] flash_write_running <= '1';

flash_addr <= write_addr + operation_counter;

flash_opcode <= WRITE_FPGA_OP;

[/INDENT][/INDENT]else -- not first time, write operation started, but wait for data_rdy

[/INDENT] if((etcmiv_data_rdy = '1') and (int_flash_en = '0')) then

[/INDENT][/INDENT] etcmiv_data_rdy_detected <= '1';

end if;

[/INDENT][/INDENT][/INDENT] if((clk_spi_flash = '1') and (int_flash_en = '0') and (etcmiv_data_rdy_detected = '1'))then -- flash_en should change only on a sck falling edge

[/INDENT][/INDENT] int_flash_en <= '1';

flash_data <= etcmiv_data;

etcmiv_data_rdy_detected <= '0';

[/INDENT][/INDENT][/INDENT] elsif(flash_done = '1') then

[/INDENT][/INDENT] int_flash_en <= '0';

flash_write_running <= '0';

[/INDENT][/INDENT][/INDENT] end if;

[/INDENT][/INDENT] end if;

[/INDENT] -- READ OPERATION

elsif((etcmiv_flash_read = '1') or (flash_read_running = '1')) then

if(etcmiv_flash_read = '1') then -- first time

[/INDENT] flash_read_running <= '1';

flash_addr <= read_addr + operation_counter;

flash_opcode <= READ_FPGA_OP;

flash_data <= "ZZZZZZZZ";

[/INDENT][/INDENT] else -- not first time, read operation started

[/INDENT] if((clk_spi_flash = '1') and (int_flash_en = '0'))then -- flash_en should change only on a sck falling edge

[/INDENT][/INDENT] int_flash_en <= '1';

[/INDENT][/INDENT][/INDENT] elsif(flash_done = '1') then

[/INDENT][/INDENT] int_flash_en <= '0';

flash_read_running <= '0';

etcmiv_data <= flash_data;

etcmiv_data_is_ready<='1';etcmiv_data_rdy <= '0';

flash_data <= "ZZZZZZZZ";

[/INDENT][/INDENT][/INDENT] end if;

[/INDENT][/INDENT] end if;

[/INDENT] -- NO OPERATION

else

if(etcmiv_ready_to_get_data = '1') then

[/INDENT] etcmiv_data_rdy <= '1';

etcmiv_data_is_ready <= '0';

[/INDENT][/INDENT] elsif((etcmiv_data_rdy = '1') and (etcmiv_data_rdy_dly = '1') and (flash_data = "ZZZZZZZZ")) then -- assure etcmiv_data_rdy is active and stable, to assure etcmiv already got it

[/INDENT] etcmiv_data_rdy <= 'Z';

etcmiv_data <= "ZZZZZZZZ";

[/INDENT][/INDENT] end if;

flash_data <= "ZZZZZZZZ";

flash_opcode <= X"0";

flash_addr <= X"000000";

int_flash_en <= '0';

flash_erase_running <= '0';

flash_read_running <= '0';

flash_write_running <= '0';

[/INDENT] end if; -- operation

end if;

end process; -- flash_p