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Altera_Forum
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15 years ago

Tip/suppornt on debugging a VHDL project on Altera

Hi I have some experience on hdl coding, but none on FPGA debugging. (which does not necessarily mean the problem may not be in my HDL coding... ;) ) I´m facing a weird (imho) situation ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Another thing I just noticed - rst isnt in the process sensitivity list, so simulations wont reset signals properly, or at least you'll get a simulation/FPGA mismatch. The FPGA will have an async reset but the simulation will have a synchronous one.