timing simulation

bonjour

I try for one day to do a simulation timing

The project is only a count16 write in VHDL

the RTL simulation is ok but in Gate Level Simulation every times are set to 0ps and waves are like a RTL simulation. (no delay between clock and outputs )

I forget something ...

I use Quartus10.1SP1 web edition with modelsim Altera starter 6.6d and the device is MAXII

can you help me?

thanks