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Altera_Forum
Honored Contributor
Honored Contributortiming simulation
bonjour I try for one day to do a simulation timing The project is only a count16 write in VHDL the RTL simulation is ok but in Gate Level Simulation every times are set to 0ps and waves are ...
Altera_ForumHonored Contributor
Honored Contributorare you running the gate level simulation yourself or with NativeLink? are you including the delay file (.sdo?) in your simulation?
