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Altera_Forum
Honored Contributor
Honored ContributorTiming Simulation with Altera-Modelsim
Hello to all, I'm new at working on CPLD in VHDL. Fortunately, I knew this language from University and I can understand and write it quite well. Maybe, the greatest difficulties are the setting...
Altera_ForumHonored Contributor
Honored Contributora timing simulation will execute much slower than an RTL simulation. its possible that your timing simulation results will match RTL simulation results, even if static timing is not met. the stimulus to your design under test hasn't exercised the worst case path that timing analysis flagged.
you shouldn't have to make a new test bench for a timing simulation.
