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Altera_Forum
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15 years ago

Timing Simulation with Altera-Modelsim

Hello to all, I'm new at working on CPLD in VHDL. Fortunately, I knew this language from University and I can understand and write it quite well. Maybe, the greatest difficulties are the setting...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

your timing/gate level simulation should also have a test bench which instantiates the gate level netlist of your project. the idea is basically the same as RTL simulation, except all of your HDL is compiled into a single HDL netlist which is the .v(h)o file.