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Altera_Forum
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8 years ago

Timing Simulation error in Quartus prime 16.1

I wanted to run timing simulation for a multiplier i designed. However after successful functional simulation, the tool is giving an error while running timing simulation i.e:# ** Error (suppressibl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

From the Error message it looks like you are missing the .sdo file.

What device are you targeting ?

Gate-level timing simulation is supported only for the Arria II GX/GZ,Cyclone IV, MAX

II, MAX V, and Stratix IV device families.. Use Timing Analyzer static timing analysis

rather than gate-level timing simulation.

Ref:

https://www.altera.com/en_us/pdfs/literature/hb/qts/qts-qps-handbook.pdf

Page 1466

Best Regards,

arslanusman2003

(This message was posted on behalf of Intel Corporation)