Timing Question

When you want to synthesize a design with output ports that are changed in a clocked process, you can't directly assign out ports from the process. The synthesizer considers that the signal on the output port needs to be read back by the hardware in order to maintain its state during the clock cycle. There are two ways around this:

[list][*]declare the port as 'BUFFER' instead of 'OUT'. This is usually considered to be the bad solution (and I agree) because it makes things more complicated (to stay polite) when combining different components. 'BUFFER' is a kind of viral attribute that you need to propagate everywhere in your design when you start using it[*]use an internal signal. Connect that internal signal to the out port outside of the process, and only assign values to that internal signal inside the process[/list]Here is an example of the latter:

ARCHITECTURE one OF adc IS
    SIGNAL cs_buffer: STD_LOGIC;
BEGIN
    cs <= cs_buffer;
    PROCESS (clk_in)
        VARIABLE count: INTEGER RANGE 0 to 21;
    BEGIN
        cs_buffer <= '1'