Timing Question

I just ran your code in modelsim and I see the clk_out toggling. Are you sure that you provide a valid clock on the input?

I also have some advice about your code:[list][*]You should use std_logic and std_logic_vector types in your code, they provide better options for simulation.[*]You should also manually wrap your counter to make it wrap back to 0. The simulator will complain when you try to reach 22, and the synthesizer will probably generate a 5 bits counter which will roll over every 32 cycles instead of 22.[*]You should also buffer your outputs through signals, your code is not synthesizable in this state.[/list]