Timing Question

I am not clear about your issue. is it timing of serial data with its clk? or serial to parallel conversion inside cpld?

for serial data out transmission you will need to generate your serial data and its serial clk in same process.The process being clked by another suitable clk.

normally your counting to be at twice serial clk speed. A good practice is make clk transition in the middle of data time slot.

-- on the clked process
   case count is
 
      when 0 => seial_data <= reg_bit(0); serial-clk <= '0';
      when 1 => serial_data <= reg_bit(0);serial_clk <= '1';
 
      when 2 => serial_data <= reg_bit(1);serial_clk <= '0';
      when 3 => serial_data <= reg_bit(1);serial_clk <= '1';