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Altera_Forum's avatar
Altera_Forum
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8 years ago

Timing parameters of USB Blaster 1

I'd like to constrain the timing of the JTAG interface of my Arria 10 design for a USB Blaster Rev C (note: not USB Blaster II). However, the documentation doesn't mention any details about the timin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

The problem looks to me as over-engineering. USB Blaster is really slow (6MHz TCK) you have nearly half cycle setup and hold time according to JTAG design principle.

Most real world JTAG problems are caused by insufficient signal integrity and not fixed via timing constraints.

I would expect that even maximum 24 MHz JTAG of USB Blaster II runs safely without timing constraints, but I don't use it yet.