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Altera_Forum
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8 years ago

Timing parameters of USB Blaster 1

I'd like to constrain the timing of the JTAG interface of my Arria 10 design for a USB Blaster Rev C (note: not USB Blaster II). However, the documentation doesn't mention any details about the timin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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I want to ensure that JTAG timing is met when there is a Signaltap instance in the design. From the timequest timing analyzer cookbook (https://www.altera.com/documentation/mwh1452708879095.html#mwh1452708874207):

And then some code follows that apparently uses the timing parameters given in the handbook of the USB Blaster II.

The TDO port, for example, is driven by the Signaltap logic (through the TDOUSER input of the altera_internal_jtag) as far as I can see from the Technology Map Viewer. Or am I getting this wrong?

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jtag not being part of core logic was not constrained but since quartus Pro things changed (not sure what is going on here). See this link:

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd07182016_788.html