Honored Contributor
Honored ContributorI want to ensure that JTAG timing is met when there is a Signaltap instance in the design. From the timequest timing analyzer cookbook (https://www.altera.com/documentation/mwh1452708879095.html#mwh1452708874207):
--- Quote Start --- Many in-system debugging tools use the JTAG interface in Altera FPGAs. When you debug your design with the JTAG interface, the JTAG signals TCK, TMS, TDI, and TDO are implemented as part of the design. Because of this, the TimeQuest analyzer flags these signals as unconstrained when an unconstrained path report is generated. [...] You can constrain the JTAG signals by applying the following SDC commands: ... --- Quote End --- And then some code follows that apparently uses the timing parameters given in the handbook of the USB Blaster II. The TDO port, for example, is driven by the Signaltap logic (through the TDOUSER input of the altera_internal_jtag) as far as I can see from the Technology Map Viewer. Or am I getting this wrong?
