Forum Discussion
NShan12
Occasional Contributor
5 years agoTiming issues on DFF feedback loop.
Hello,
I wanted to know if the output of DFF in the attached design leads to any timing problems.
What happens to DFF output if both Preset and Clear are active at the same time?
CLK is 32 MHz....
KhaiChein_Y_Intel
Regular Contributor
5 years agoHi,
It is difficult to investigate the root cause without the design to reproduce the error.
I tried to create a small test case to help you understand how the preset and clear works in the DFF. Hope it helps.
Thanks
Best regards,
KhaiY