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NShan12's avatar
NShan12
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Timing issues on DFF feedback loop.

Hello, I wanted to know if the output of DFF in the attached design leads to any timing problems. What happens to DFF output if both Preset and Clear are active at the same time? CLK is 32 MHz....
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Could provide the simple test case so that I could compile and simulate to reproduce the behavior?


Thanks

Best regards,

KhaiY


NShan12's avatar
NShan12
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hello,

Sorry for the delayed reply. I was trying to create relevant test vector inputs but was unsuccessful.

To explain the issue: The screenshot of the schematic in earlier post belongs to a file in 3rd level of instantiation. Some of the inputs to this block are generated from other blocks. Thats the reason its difficult to regenerate the behaviour without the complete project and complete set of input test vectors.

The test vectors (as mentioned earlier) are given to top level input pins.

Do you know any other way to continue solving the issue?

I can understand its difficult to answer without having the schematic and test vectors, but I would like to know if I can perform any tests as per your suggestion and post the results here.