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Honored Contributor
Honored ContributorTiming for MAX 10 ADC Control Core Only interace logic
I'm trying to create the necessary external logic to control a MAX10 ADC Control Core Only instance. The timing in figure 8 of the UG-M10ADC User Guide does not define the relationship between comma...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hi, Attached is a vhdl file that I got working. --- Quote End --- I need to post an update to this! The code I posted above works in simulation (once you get past simulation tools problems), but does NOT work in hardware. Issue: The ADC does not work if the two input clocks into the ADC are the same clock! Solution: use a different clock, or just invert the clock_clk clock.
