Timing for MAX 10 ADC Control Core Only interace logic

Hi, I'm only just learning this myself, and it's taken me the best part of 3 weeks to get it simulating, so take my input with caution.

1) I think the two clocks can be separate. The PLL clock has to come from the PLL whether you want it to or not. The other clock could be a different frequency. Say, 8MHz for the logic, and 2MHz for the PLL. I'm using the same clock for both.

2) I don't think command_startpacket, command_endofpacket are relevant for the Core Only ADC, or at least I've not found a use yet. I have them tied low.

3) command_valid seems to be the important signal. It seems that when you take it high and HOLD it high, some time later command_ready pulses high for one clock. (I assume this is the IP clock). Thereafter command_ready and response_valid pulse high both pulse high together for one clock, at the rate you selected when you created the IP core. response_channel() and response_data() are both valid for one clock at the same time as response_valid.

4) It appears you can change command_channel on the fly.