Forum Discussion
Seadog
Occasional Contributor
Occasional ContributorTiming error on Arria 10 PCIe core design
I have an Arria 10 design with a PCIe core (hard-IP, 8 lanes, gen 3, Avalon memory-mapped, w/ DMA). The only timing errors I am getting are related to the reset generated by the PCIe core. The rese...
BoonT_Intel
Frequent Contributor
Frequent ContributorHi Sir,
Sorry, I just learned from a member that familiar with timing, he said removing the SDC will only masking the issue but not removing the issue.
He mentioned for IP, usually the removal/recovery violation for reset signal that come from external can be safely ignore. This is because the IP already synchronizing the reset.
