Forum Discussion
Seadog
Occasional Contributor
Occasional ContributorTiming error on Arria 10 PCIe core design
I have an Arria 10 design with a PCIe core (hard-IP, 8 lanes, gen 3, Avalon memory-mapped, w/ DMA). The only timing errors I am getting are related to the reset generated by the PCIe core. The rese...
BoonT_Intel
Frequent Contributor
Frequent ContributorI compile the arria 10 PCIe design and I don't see the timing issue. If the timing violation is come from the core, I should see the same from my design as well. Do you add any user logic to the reset of the IP core?
