Forum Discussion
Seadog
Occasional Contributor
Occasional ContributorTiming error on Arria 10 PCIe core design
I have an Arria 10 design with a PCIe core (hard-IP, 8 lanes, gen 3, Avalon memory-mapped, w/ DMA). The only timing errors I am getting are related to the reset generated by the PCIe core. The rese...
BoonT_Intel
Frequent Contributor
Frequent ContributorHi Sir,
Did you try this in the generated example design and get the same timing violation?
