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Altera_Forum
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17 years ago

Timing Contraint on latch

Anyone knows how to constraint the latch related circuitry? I attached a pdf that show the diagram. The clock is running at 10MHz and the timing requirements from input to output is 80nSec.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I know using latch is not good design and do not want to use. Unfortunately, I must use it for my application. I need to find out how I can constraint these latch. I was thinking of using set_max_delay, but I'm not sure whether this would do it since set_max_delay is used for combinatorial logic path.