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Altera_Forum
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17 years ago

Timing Contraint on latch

Anyone knows how to constraint the latch related circuitry? I attached a pdf that show the diagram. The clock is running at 10MHz and the timing requirements from input to output is 80nSec.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

What is the purpose of this latch? Generally, using latches is not good design practice.

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Anyone knows how to constraint the latch related circuitry? I attached a pdf that show the diagram. The clock is running at 10MHz and the timing requirements from input to output is 80nSec.

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