Occasional ContributorI have outputs from one FPGA to another FPGA. Outputs are clocked out of one FPGA and is completely combinational in the other FPGA. Can I set false path to these outputs.
ContributorYes. Set false paths to any input or output signals that you don't need the timing analyser to consider.
Cheers,
Alex
Occasional ContributorHi Thanks for the Reply.
How can we determine the signals that doesn't require timing analysis?
ContributorAny signal in to or out of the device that is asynchronous - i.e. doesn't have an associated clock.
Cheers,
Alex
Occasional ContributorHi Thanks for the reply.
