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SK_VA's avatar
SK_VA
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Timing constraints to asynchronous output

I have outputs from one FPGA to another FPGA. Outputs are clocked out of one FPGA and is completely combinational in the other FPGA. Can I set false path to these outputs.
a_x_h_75's avatar
a_x_h_75
Icon for Contributor rankContributor
7 years ago

Yes. Set false paths to any input or output signals that you don't need the timing analyser to consider.

Cheers,

Alex

SK_VA's avatar
SK_VA
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Hi Thanks for the Reply.

How can we determine the signals that doesn't require timing analysis?