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Altera_Forum
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14 years ago

Timing constraint problem while using altera ipcore

Hello everyone, I met two problems while using altera ipcores: fir core and fft core(in Straitix III system). The sample clk in my project is 187MHz, and I’ve checked the user guide that both ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Thank you Daixiwen, I would consider about your advice if necessary.Thank you again for your kind help these days.