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Altera_Forum
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14 years ago

Timing constraint problem while using altera ipcore

Hello everyone, I met two problems while using altera ipcores: fir core and fft core(in Straitix III system). The sample clk in my project is 187MHz, and I’ve checked the user guide that both ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Unfortunately I don't know the FIR's internals, I design my own filters without using the megacore. Can the coefficients loading be done in a different clock domain?

Did you have a loot at the timing advisor (Tool menu)? It con give you some ideas about settings to change to increase the fmax.

Do you have some options to register the core's inputs and outputs? If yes, enable them.