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Honored Contributor
Honored ContributorTiming constraint problem while using altera ipcore
Hello everyone, I met two problems while using altera ipcores: fir core and fft core(in Straitix III system). The sample clk in my project is 187MHz, and I’ve checked the user guide that both ...
Altera_ForumHonored Contributor
Honored ContributorOnce you have constrained your designs clocks, Timequest should use their frequencies in its analysis. Just create the input clocks in your .sdc file with the correct frequency/period.
If the fitter isn't able to meet the timing requirements, you may need to increase the pipeline level. I don't know if it is configurable in the fir and fft cores.
